Senior Compiler Engineer at Nvidia, specializing in LLVM toolchains and RISC-V architecture. Carnegie Mellon graduate with expertise in compiler optimization, system software, and edge computing.
Maintaining and optimizing an LLVM toolchain for RISC-V embedded CPU with custom extension.
Led LLVM/Clang toolchain optimization for RISC-V CPU cores, contributing to upstream LLVM. Specialized in middle and backend passes, instruction selection, and scheduling optimization.
B.Sc. Computer Science (GPA: 3.96/4.0)
Achievements: Qatar Campus Scholar, Top-of-class GPA, College & University Honors, Full scholarship
M. Nurul-Hoque and K. A. Harras, (2022). "WebAssembly for Edge Computing: Potential and Challenges." IEEE Communications Standards, 6(2), 45-52.
M. Nurul-Hoque and K. A. Harras, (2021). "Nomad: Cross-Platform Computational Offloading and Migration in Femtoclouds Using WebAssembly." In Proceedings of the IEEE International Conference on Cloud Engineering (IC2E '21) (pp. 178-189).
A. Essameldin, M. N. Hoque and K. A. Harras, (2020). "More Than The Sum of Its Things: Resource Sharing Across IoTs at The Edge." In Proceedings of the IEEE/ACM Symposium on Edge Computing (SEC '20) (pp. 324-336).